Notes on chip init scripts

Type1:

 0A - 0C XX YY 01:  XX - mem, YY - core clock, base 2.25Mhz (=27Mhz/12?)
 12 - 12 12 ?? ??:  Mem timings?  12/12 for DDR, 22/22 for SDR... 23/23 - 8500DV

 0F, 10, 11 - Mem timings?

Radeon 7500/8500:
 0C - 33 A4 00 04 - Retail
 0C - 33 BC 00 04 - OEM/LE

Type2 (Rage128):

80/60 MHz @ 14.32 Mhz clock:
 Reg0[0130] <- 50
 Reg0[0140] and 00000000 or 13008301
 Reg0[02E8] and 00000000 or 08900262
 Reg0[02EC] and 00000000 or 0F7D7BE8
 Reg0[0B00] and FFFFFFF0 or 00000010

90/90 Mhz @ 29.5 Mhz clock:
 Reg0[0130] <- 60
 Reg0[0140] and 00000000 or 50004300
 Reg0[02E8] and 00000000 or 08900393
 Reg0[02EC] and 00000000 or 173BB9DC
 Reg0[0B00] and FFFFFFF0 or 00000021

103/103 Mhz @ 29.5 Mhz clock:
 Reg0[0130] <- 70
 Reg0[0140] and 00000000 or 70004300
 Reg0[02E8] and 00000000 or 09A0020B
 Reg0[02EC] and 00000000 or 0D4B6A5A
 Reg0[0B00] and FFFFFFF0 or 00000031

118/140 MHz @ 27 Mhz clock:
 Reg0[0130] and FFFFFF00 or 00000054
 Reg0[0140] and 00000000 or C0004300
 Reg0[02E8] and 00000000 or 09A002C7 - mem timigs?
 Reg0[02EC] and 00000000 or 1211908F - ? mem
 Reg0[0B00] and FFFFFFF0 or 00000042